The present invention pertains to the general technology field of embedded computer systems. More specifically, the present invention pertains to the field of bus architecture for embedded computer systems.
A bus architecture of a computer system conveys much of the information and signals involved in the computer system""s operation. Typically, a host bus is used for connecting a central processing unit (CPU) to a memory and another bus is used for connecting the CPU to other elements such as input/output units. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In many hardware applications, such as, graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate. In many computer system architectures of today, the majority of the above mentioned subsystems reside on the computer system""s expansion bus.
The expansion bus is generally used as a method of adding functional components to the computer system. The functional components are physically coupled to the expansion bus, and use the expansion bus to communicate and exchange information. Dedicated bus-based designs (designs specifically conceived to operate from an expansion bus) typically embody the functional components. The PCI (Peripheral Component Interconnect) bus is an industry standardized, widely known, and widely supported example of an expansion bus architecture.
In embedded processor systems, however, some peripheral devices are not connected to expansion buses. Rather, some peripheral devices may need to be connected to the processor local bus itself due to performance constraints and other design factors. FIG. 1 shows a typical implementation of an embedded controller system 100. Embedded controller system 100 includes a microprocessor 110 that shares the host bus 120 with two other bus mastering devices 130a-130b and two other slave devices 140a-140b. Bus mastering device 130a also includes a custom interface 135 for interfacing to another device. Embedded controller system 100 further includes a bus arbiter 150 for arbitrating bus access requests.
One problem associated with the implementation as shown in FIG. 1 is that the bus mastering devices 130a-130b may significantly affect the load on the host bus 120. Increased loading on the host bus 120 implies that the capacitance on the bus 120 is higher. Thus, the timing (xcfx84=1/RC) of the host bus 120 may be affected. In other words, the more devices are added to the host bus 120, the slower the processor. In order to achieve higher performance, the number of loads on the host bus must be as minimal as possible. As a result, the throughput of the entire embedded processor system 100 is reduced. Thus, what is needed is a method and system for adding more devices on the host bus without affecting the throughput of the embedded processor system.
Another drawback associated with the embedded processor system 100 is that a large number of I/O pins may be required for the custom interface 135. For example, assuming that the host bus has a 32-bit address bus and provides access to 4 GB of addressable space. If the custom interface 135 needs to access all of this available memory, then the custom interface also has to provide 32-bit addresses, thus increasing the number of I/O pins required. As the number of I/O pins available on a chip is limited, there exists a need for a method and system for providing an interface to multiple off-chip devices without significantly increasing the number of I/Os.
Yet another drawback of the implementation of system 100 is that, while the host 120 bus is being utilized by one master (e.g., bus mastering device 130a), another master (e.g., bus mastering device 130b) requesting access to the bus 120 has to monitor the bus activity all the time. Sometimes, bus activity monitoring is needed even if the master does not require access to the bus at all. From a power management standpoint, the implementation of system 100 is not very effective. Consequently, what is needed is an interface that consumes very little power.
Accordingly, the present invention provides a multi-modal and multi-channel direct memory access (DMA) controller that supports both fly-by mode and flow-through modes of operation. In one embodiment of the invention, the DMA controller is a bus mastering device that supports the following modes of operation: (1) fly-by mode, (2) flow through mode, and/or (3) dual cycle mode. In the present embodiment, the DMA controller operates in the xe2x80x9cfly-byxe2x80x9d mode for devices that require low access latency. The DMA controller operates in the xe2x80x9cdual-cyclexe2x80x9d mode for devices that have a relatively low performance in comparison to the host bus. The DMA controller operates in the xe2x80x9cflow-throughxe2x80x9d mode for devices that have a high performance but do not require low access latency.
The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus.
In one embodiment of the present invention, the DMA controller has address-generation logic which provides access to the entire addressable range of the host bus. What is necessary from the bus mastering device point of view is the ability to access the address registers, the terminal count registers and the data registers of the DMA controller. In the present embodiment, device firmware would be responsible for writing the appropriate host address range into the address and count registers. Using shared busses on the device side of the DMA controller and addressing only the DMA registers reduce the number of I/O (input/output) required in the chip.
Embodiments of the present invention include the above and further include a multi-modal direct memory access (DMA) controller that has a front-end interface for communicating control signals and data with a host bus of a data processing system; a first back-end interface for communicating first control signals with a first bus-mastering device, and a second back-end interface for communicating second control signals and data with a second bus-mastering device. In one embodiment, the first control signals are operable to cause the DMA controller to enter a fly-by mode whereby data are directly communicated between the first bus-mastering device and the host bus. The second control signals are operable to cause the DMA controller to enter a flow-through mode whereby data are communicated between the second bus-mastering device and the host bus via the DMA controller.